1. Field of the invention
The present invention relates to a semiconductor memory, and more specifically to an ultra violet erasable non-volatile semiconductor memory (called to"EPROM" in this specification).
2. Description of related art
FIG. 1 is a diagram illustrating a construction of the most typical conventional CMOS tristate output circuit. Referring to FIG. 1, this conventional output circuit 40 is constituted of an NAND circuit 42, a NOR circuit 44, driver gate input control circuits 46 and 46A, and a driver composed of a P-channel MOS transistor 47 and an N-channel MOS transistor 48. Outputs of the driver gate input control circuits 46 and 46A are connected to gates of the P-channel MOS transistor 47 and the N-channel MOS transistor 48, respectively, which have a drain thereof connected to each other. A connection node between the drains of the P-channel MOS transistor 47 and the N-channel MOS transistor 48 is a final output 49 of the output circuit.
A signal applied to an output buffer input 41 is applied to one input of the NAND circuit 42 and one input of the NOR circuit 44, respectively. The other input of the NOR circuit 44 is connected to receive an output buffer activation signal 45, and the other input of the NAND circuit 42 is connected to receive a signal by inverting the output buffer activation signal 45 by an inverter 43.
Now, operation of the above mentioned conventional output circuit will be described.
First, when the output buffer activation signal 45 is a low level, the output buffer input 41 is transferred through the NAND circuit 42 and the NOR circuit 44, and further is applied to the gates of the P-channel MOS transistor 47 and the N-channel MOS transistor 48 after the inclination of a rising waveform or a falling waveform of the signal is sharpness-deteriorated by the driver gate input control circuits 46 and 46A. Incidentally, the driver gate input control circuits 46 and 46A are formed of for example normally-on MOS transistors.
At this time, if the output buffer input 41 is at a high level, the output of the NAND circuit 42 is brought to the low level, so that the P-channel MOS transistor 47 is turned on. Furthermore, the output of the NOR circuit 44 is also brought to the low level, so that the N-channel MOS transistor 48 is turned off. Thus, the final output 49 is brought to the high level.
On the other hand, if the output buffer input 41 is at a low level, the output of the NAND circuit 42 is brought to the high level, so that the P-channel MOS transistor 47 is turned off. Furthermore, the output of the NOR circuit 44 is also brought to the high level, so that the N-channel MOS transistor 48 is turned on. Thus, the final output 49 is brought to the low level.
In addition, if the output buffer activation signal 45 is a high level, the output of the NAND circuit 42 is fixed to the high level, and the output of the NOR circuit 44 is also brought to the low level. Accordingly, both of the P-channel MOS transistor 47 and the N-channel MOS transistor 48 are off. Thus, the final output 49 is brought into a high impedance condition.
Next, a writing and a write verifying of the EPROM will be described with reference to FIG. 2.
Generally, the EPROM requires two external power supplies, namely, a reading power supply voltage (called Vcc) and a writing power supply voltage (called Vpp). It is the mainstream that Vcc is 5 V, similarly to other integrated circuits, and Vpp is 12.5 V at present.
First, at the time of writing, the voltages are risen up, from Vpp=Vcc=5.0 V at the time of an ordinary reading, to Vpp=12.5 V and Vcc=6.5 V (for example, even in a product having an ordinary reading Vcc range of 5.0 V .+-.0.5 V, Vcc is set to 6.0 V or in some time to 6.5 V in order to check a margin of a writing depth of a memory cell).
Thereafter, an address and data are inputted, and a chip enable signal CE (low active) is brought to a low level, (CE="L") when an output enable signal OE is at a high level (OE="H"), so as to execute a writing (this corresponds to "PROGRAM" in FIG. 2). At the time of CE ="H" and OE="L", the write verifying (which is called a "program verify" as another expression, and which is simply called a "verify") is executed.
The "verify" is a mode in which the data written into the memory is read out in order to confirm the completion of the writing. An internal circuit of the integrated circuit operates in completely the same manner as the ordinary reading mode. In other words, it is equivalent to the reading mode in the case of a high Vcc.
Thereafter, an operation similar to the above mentioned operation is repeated until a last address (while Vpp and Vcc are fixed). Thus, the writing is completed.
Conventionally, the program (the period of CE="L") is a few hundred microseconds, and the program verify (OE="L") is a few microseconds.
As mentioned above, in the verify in the course of the writing operation of the conventional EPROM, Vcc is set to a level higher than a rated voltage for the ordinary reading, in order to check the margin of the writing depth of the memory cell.
Because of this, a problem has been encountered in which, fluctuation of Vcc and a ground level (GND) caused by a change of output data of the integrated circuit (power supply noise) becomes larger than that in the ordinary reading, and this fluctuation is propagated to a sense amplifier and an address buffer, thereby causing a data verify error.
More specifically, a closed loop is formed among the address buffer .fwdarw.the sense amplifier .fwdarw. the output buffer, so that oscillation occurs Even if the period of the verify is elongated, the output of the integrated circuit cannot be properly read out.